Self-check number generation

ABSTRACT

A self-check number generating device for generating/validating check numbers associated with a data entry/verification or data transmission system. The generating device is operable in a plurality of modes and may be used for generating or merely validating a check number to be appended to a data number or word.

United States Patent 51 3,686,629 Yu 51 Aug. 22, 1972 [54] SELF-CHECK NUMBER GENERATION 3,105,636 10/1963 Greene ..340/146.1 X 3,163,748 12/1964 Schafer etal ..340/146.1 X [72] Invent Frank Burlmgmn Mass 3,384,902 5/1968 Schroder et al. ..340/146.1 [73] Assignee: Honeywell Inc., Minneapolis, Minn 3,460,l 17 8/1969 Cohn et al. ..340/146.1 [22] Filed: June 16, 1970 3,517,385 6/1970 Katsuragl ..340/l46.1

[21] Appl. No.: 46,711 Primary Examiner--Charles E. Atkinson AttorneyFred Jacob and Leo Stanger [52] US. Cl. ..340/l46.l J 57 1 ABSTRACT [51] Int. Cl ..G06f 11/10 [58] Field of Search ..340/14e.1 AJ; 235/617 A A Self-check number generatmg devlce for g ing/validating check numbers associated with a data [56] References Cited entry/verification or data transmission system. The generating device is operable in a plurality of modes UNITED STATES PATENTS and may be used for generating or merely validating a 3,526,875 9/1970 Jourdan ..340/146.1 umber be appended to a data umber 3,484,744 12/ 1969 Gertler et a1. ..340/146.1 3,098,994 7/1963 Brown, Jr. ..340/ 146.1 14 Claim, 27 Drawing Figures PROGRAM 46 DIGIT WEIGHT V50 DECODER REG|STE(F\;[/)0OUNTER D|G|T (B) ADDER GATES ACCUMULATOR REGISTER TRIGGER FOR T FLlP-FLQPS T FLlP-FLOPS (A) Z48 (T6) CCU I/o DCA CARRY GENERATION INTERFACE BUS INTERFACE (C) AND (D) 40 L CONTROLS VALIDATE PULSE GENERATION COMPARATOR (AB) CHECK men ERROR \60 Patented Aug. 22, 1972 3,686,629

22 Sheets-Sheet 1 MAIN CONTROL STATION UNIT (MGS) 7 4 [I2 7 M05 AUXILIARY CONTROL PANEL T CONTROL CONTROL KEYBOARD CONTROL KEYS ,24 KEYBOARD DATA KEYS 1/0 INTERFACE 25 II I Y 7 KEYBOARD TAPE SELF-CHECK 00A 20 DcA NUMBER DcA TAPE 22 FIG 1 I/O BUS STROBE LINES LINE BIs ADS OPS 005 ms ICS FOI DATA ADI-)6 PBI TMD-X- PRQ ERR F02 DATA AD2 PB2 TRB-X- lDP-X- MIN F03 DATA AD3* P83 EOD-X- ALP-X- MDc MULT| F04 DATA AD4-X- P84 TAK-X- BUR-)6 DUP F N I N F05 DATA PBS-X- VER-X- SKP L'NES F06 DATA PRL AGN-X- LZK F07 DATA TERI lSP-X- TMW* F08 DATA TER2* |LZ* REW-X- F09 DATA TMF-X- ERo RLK-X- ADv ADDRESS vAI ID INT INITIALIZE PDA COMMON TIMING SINGLE TsM TRAFFIC sTATE MODIFY FUNCTION LINES HSC HIGH SPEED COMMUNICATOR WMD ccu IN WRITE MODE vMD ccu IN vERIFY MoDE INH INHIBIT FIG. 2 FRANK K. /nven/or Patented Aug. 22, 1972 22 Sheets-Sheet 4 CHECK DIGIT DCA ACTIVATED CHECK PROG. ans

IF I63, SET w=| IF w SET w=2 TRANSFER DIGIT TO B REGISTER FIG. 5

ADD I TO AOI ADD B TO A DECREMENT W YES PROGRAM (\0/ n IO- A CHECK DIGIT FRANK K. YU

Patented Aug. 22, 1972 22 Sheets-Sheet 6 zorcmom .565 xomIo hmm mus

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22 Sheets-Sheet 1O REGISTER 1 REGISTER 2 BGSIO XNU TOI BIS TMIIO (TITS- REGISTER 3 TOI CONDITIONED REGISTER 4 FDA FPS ao4|0 RSB FRANK K YU lm enfor A I By lg/1;, flu z; a

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Patented Aug. 22, 1972 3,686,629

22 Sheets-Sheet l2 ACCUMULATOR FLOP TRIGGER ACCUMULATOR TGIIA 00 PO PDA GHQ 04 'AOHO CVT RSA

TGZIA POI PDA TGZIO J02 AOZIO CVT RAZIO RSA TGZIA POI TGBIO CVT RASIO RSA POI

TG4IO CVT FRANK K. YU

. p lnven jor lam/1 y RSA Patented Aug.- 22, 1972 22 Sheets-Sheet l 3 IN OE N00 Qwox 2 o FRANK K. YU

Inventor By 44" 1'7 Allorney Patented Aug. 22, 1972 3,666,629

22 Sheets-Sheet l6 XNU ERRIO PDA ILHIO BB l H FIG; 7M

FRANK K. YU

In van for 

1. In a data processing system having means for generating program signals and data signals, a data verification device comprising: a. a register for receiving said data signals, b. an accumulator, c. means connecting said register and said accumulator, d. a comparator, e. means connecting said register and said comparator, and f. means responsive to said program signals for transferring said data signals from said register to said accumulator or for transferring said data signals to said comparator.
 2. A system as set forth in claim 1 wherein said means responsive to said program signals is a program decoder.
 2. an accumulator, and
 3. means responsive to said program information for transmitting said data from said register to said accumulator.
 3. A system as set forth in claim 2 further comprising a weight counter and means responsive to said weight counter for causing the contents of said register to be transferred to said accumulator a plurality of times.
 4. A system as set forth in claim 3 where the number of said transfers is established by said program decoder.
 5. A system as set forth in claim 4 wherein an input to said weight counter is connected to an output of said accumulator and wherein the contents of said accumulator change the contents of said weight counter.
 6. A system as set forth in claim 1 wherein said program signals establish the existence of a check-digit in said accumulator.
 7. A system as set forth in claim 1 wherein said means for generating program signals and data signals generates said signals alternately.
 8. A system as set forth in claim 2 further comprising an input/output bus, said program signals and said data signals being carried on said bus.
 9. A system as set forth in claim 8 wherein a check digit may be generated by said data verification device.
 10. In a data entry system comprising a central control unit, said central control unit providing program information, a peripheral input device and a bus connecting said input device and said central control unit: a. generating means connected to said bus, b. said generating means responsive to said program information on said bus to perform arithmetic operations on data on said bus, said generating means comprising:
 11. A system as set forth in claim 10 wherein said means responsive to said program information is a program decoder.
 12. A system as set forth in claim 11 wherein said data originates in said central control unit.
 13. A system as set forth in claim 12 wherein said program information and said data are interleaved on said bus.
 14. A system as set forth in claim 13 wherein said peripheral input unit is a keyboard. 